library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity fpgatester_tb is
end entity fpgatester_tb;

architecture structural of fpgatester_tb is

  component fpgatester is
  port (
    clk : in std_logic; --
    
    reset : in std_logic; --button
    direction : in std_logic; --switch
    counter_reset : in std_logic; --button
    
    motor : out std_logic
  );
	 end component fpgatester;

	signal	clk			: std_logic;
	signal	reset			: std_logic;
	signal	direction		: std_logic;
	signal counter_reset : std_logic;
	signal motor :  std_logic;
	
begin


lbl0:	fpgatester	port map (	clk		=> clk,
					reset		=> reset,
					direction => direction,
					counter_reset	=> counter_reset,
					motor => motor
			);
			
			
			


lbl1: clk		<= 	'0' after 0 ns,
		   		'1' after 10 ns when clk /= '1' else
				'0' after 10 ns;
lbl2: reset <= '0' after 0 ns,
	             '1' after 40 us when reset /= '1' else
	             '0' after 40 us;
direction <= '0' after 0 ns,
	             '1' after 20 us when direction /= '1' else
	             '0' after 20 us;

	 --pwm_test <= '1' after 0 ns;
end architecture structural;




